Non-volatile memory devices are well known in the art. For example, a split-gate memory cell is disclosed in U.S. Pat. No. 5,029,130 (which is incorporated herein by reference for all purposes). This memory cell has a floating gate and a control gate disposed over and controlling the conductivity of a channel region of the substrate extending between source and drain regions. Various combinations of voltages are applied to the control gate, source and drain to program the memory cell (by injecting electrons onto the floating gate), to erase the memory cell (by removing electrons from the floating gate), and to read the memory cell (by measuring or detecting the conductivity of the channel region to determine the programming state of the floating gate).
The configuration and number of gates in non-volatile memory cells can vary. For example, U.S. Pat. No. 7,315,056 (which is incorporated herein by reference for all purposes) discloses a memory cell that additionally includes a program/erase gate over the source region. U.S. Pat. No. 7,868,375 (which is incorporated herein by reference for all purposes) discloses a memory cell that additionally includes an erase gate over the source region and a coupling gate over the floating gate.
Historically, the above described memory cells were used in a digital manner, meaning that the memory cells had two programmed states: the programmed state (i.e., the 0 state), and the unprogrammed state (i.e., the erased or 1 state). More recently, applications have been developed for the above described memory cells in which the memory cells are programmed and erased in an analog fashion so that each memory cell can be programmed to a programmed state anywhere within a continuous analog program state range. Or, the memory cells are programmed and erased in a digital fashion, where each memory cell can be programmed to one of many possible programming states. Either way, the program and erase operations are performed incrementally (e.g., using a series of program or erase pulses, and measuring the program state between pulses) until the desired program state is achieved. In both cases, the memory cells require precise programming of their programming states.
For all the above referenced memory cells, the memory cells are configured in an array of rows and columns. The conventional technique of programming memory cells is sequential, row by row, cell by cell, starting with the first memory cell in the row, and moving on to the next memory cell, and so on one cell at a time, until the entire row is programmed. However, as critical dimensions shrink, it has been discovered that cross coupling between adjacent floating gates in the same row can result in the programming state of one floating gate being adversely affected by the programming operation on an adjacent memory cell. For example, if the first memory cell in the row is programmed, and then the second memory cell in the row is programmed, the programming of the second memory cell can change the programming state of the first memory cell through floating gate to floating gate coupling, and so on, causing unwanted programming errors to occur in some memory cells. The magnitude of adverse incremental programming is proportional to the level of programming of the adjacent cell. The higher the programming level of any given cell, the worse aggressor it becomes to its neighboring cells.
There is a need for a non-volatile memory array operational technique that reduces the amount of programming errors caused by cross coupling between adjacent memory cells.